1. Field of the Invention
The present invention relates to an output buffer circuit and semiconductor integrated circuit.
2. Description of the Related Art
There is known an inter-LSI data transmission technique in which an LSI of a transmitting side transmits a strobe signal and a data signal to an LSI of a receiving side with a suitable phase difference and the LSI of the receiving side synchronizes a transmission operation with the received strobe signal to receive the data signal.
FIG. 6 illustrates a conventional output buffer circuit and a receiving circuit for inter-LSI data communication.
As illustrated in the figure, an LSI 2 of the transmitting side includes latches 470 and 471 and output buffers 480 and 481. An LSI 3 of the receiving side includes input buffers 490 and 491 and a latch 500.
Each of the output buffers 480 and 481 includes a buffer circuit as illustrated in FIG. 1 of, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2000-332595. This buffer circuit adjusts a trough rate of an output waveform regardless of the magnitude of a load connected to the receiving side.
In such the configuration, since a threshold voltage Vref differs depending on LSI, even if such the buffer circuit is applied, a rise time and a fall time of DATA_OUT signal are varied. Accordingly, a margin of a set-up time or hold time is reduced at the receiving side.
When the set-up time or hold time is set shorter than a certain predetermined time, the output waveform is distorted to cause an erroneous operation in data transmission. When the margin of the set-up time or hold time is reduced, an increase in transmission speed is prevented. For this reason, it is required that delay time when the data signal rises should be the same as delay time when the data signal falls at the LSI of the receiving side.
The present invention has been made with consideration given to the aforementioned problem and an object of the present invention is to attain data transfer with a small number of erroneous operations and high reliability.
Moreover, another object of the present invention is to provide an output buffer circuit and semiconductor integrated circuit that can adjust a through rate in such a way that delay time when a data signal rises is the same as delay time when a data signal falls.